PWM from Chisel Book

import chisel3._
import chisel3.util._

class PWM extends Module {
    val io = IO(new Bundle {
        val pwm = Output(Bool())
    })

    def pwmfn(nrCycles: Int, din:UInt):Bool = {
        val cntReg = RegInit(0.U(unsignedBitLength(nrCycles - 1).W))
        cntReg := Mux(cntReg === (nrCycles-1).U, 0.U, cntReg + 1.U)
        din > cntReg
    }
    
    val FREQ = 50*1000*1000
    val MAX = FREQ/1000
    val mReg = RegInit(0.U(32.W))
    val upReg = RegInit(true.B)

    when (mReg < FREQ.U && upReg) {
        mReg := mReg + 1.U
    } .elsewhen (mReg === FREQ.U && upReg) {
        upReg := false.B
    } .elsewhen (mReg > 0.U && !upReg) {
        mReg := mReg - 1.U
    } .otherwise {
        upReg := true.B
    }

    val pwm = pwmfn(MAX, mReg >> 10)

    io.pwm := pwm
}

object PWM extends App {
    (new chisel3.stage.ChiselStage).emitVerilog(new PWM)
}

https://gist.github.com/tzechienchu/691fccef3c241534c42976a2d6e9402a