TC_Chu's Point

Hide or Not hide that is the question !

軟體重構或是設計時

常常提到Data Abstraction , Data hiding. 

基本上主要的目的

就是讓那些會變動的資料 與 變動資料的function 包再一起

這樣只需要把它們全部視為一個整體就好了

不過所謂的包再一起我個人不覺得是要封裝在Class or Object之內

我認為單純的擺在一起也是一種Containment.

(至於重複性 那是另一個問題)

因為一但封裝起來之後 要理解就需要打開另一個檔案

可視性就不高了

(有些Editor有提供 Inline view的功能 這樣我覺得就OK)

說到這邊 我想這就與個人的整理習慣有關了

我喜歡開放式 一目了然的 如果要盒子裝 也是半透明盒子

哈哈哈哈

所以

藏與不藏要配合自己的習慣

Zelda Skyward Sword (4)

武器包全滿了@@

SICP - Frame Model of Computation

晚上了這堂課30年

不然就比較容易理解1993,94年的Newton Script

Zelda Skyward Sword (3)

三個神殿過了

這隻也幹掉了 拿到綠色火焰了

目前要去拉聶爾沙海

Starting Go Language

2021-52

最近在讀Scala, Scheme(Lisp),Go . 然後發現

Lisp實在是精實的可以

C 在當時與Fortran Cobol比較起來也是精實的設計

Go 認真看來跟 C 在當時的情況一樣

C要解決的是Hardware -> OS (System progrm) 的問題

Go 我想要它要解決的是Multiple-Core CPU 的問題

至於 Scala  實在是好複雜

(不過過去透過Scala 學到很多 Computer Language 相關的議題

也加強我對FP的信心)

Learning Scala Programming

只讀了一半 主要是要看懂Chisel 後面的Akka Web相關的先擺著

Essential 555 IC

2021-51

https://zh.wikipedia.org/zh-tw/555%E8%A8%88%E6%99%82%E5%99%A8

這顆IC 1971年誕生 只比我小五歲

現在還是一年有幾千萬顆的用量

是我的模範

Computer Task is about Design the Domain Language for Each Layer

2X年的工作經驗也不過就是如此

Chisel HDL Starter's Guide

2021-50

How to Makes Internal IT System for Mobile Phone over Internet

Pre-Condition:

You have a IT System DB + API + Web Frontend

But it is inside your intranet. (That is good for security)

But

You customer want to use App to interact with you

How ?

You can Move the system to AWS add App face API call it Done 

I don't like it. Because it expose to much to the internet

So 

I propose a piggyback system

There are a db with 2 table on AWS 

a.View table for app read only

b.Command table for app action on internal db.(Create, Update, Delete)

Then you need to add 2 API in you intranet system

a.Aggregator that watch the tables and aggregate the data every X seconds.

   then send to View table on AWS

b.Dispatcher that watch the Command table on AWS and

   run the pending command use the original API

Since the View table is read only it is easy to build with append only and back with redis cache.

There is a X in the system that determine the turn around time that user Interact with your system.

So when you design your app need to take that into consideration.

You can cover that with UI trick or add a notification to tell App to read the update

十三夜 樋口一葉小說選

2021-49

Zelda Skyward Sword (2)

看人家過關是一回事

自己過關又是一回事

手抖就是難啊

眼脫也是難啊

MIT 6.001 SICP

1986年 民國 75年 台北工專電子科4年級的我 

那時已經不太在學校上課

主要都在寫程式(用Fortran or Pascal)

光華商場能買到盜版的MatLab, Mathematica, Smalltalk,Prolog.

都買回家研究了一下 GoldenCommon Lisp 也有

不過實在是基本功不夠 無法體會 Lisp的高深

後來轉向Digital Logic Design

那時也跟學校教授 做Bit -Slice Computer

其實現代的Computer Architecture

基本上在198x年代 就幾乎完備了

Pipeline, Cache, Register File

RISC-1 應該也是那時候就有了

10年前知道SICP這本書之後

一直想找時間看SICP (Structure and Interpretation of Computer Program)

最近找到Video

看了第一集 好像回到年輕時代

學生還是用紙筆 作筆記沒有筆記型電腦

教授 開宗明義

Computer Science is Wrong 

It is not a Science and It is not about Computer. 

真是太棒了

就跟 

Data Science一樣 哈哈哈哈哈

另外

腦袋空空的 比較能夠吸收新知

https://www.youtube.com/playlist?list=PLE18841CABEA24090

 

誰要打國產疫苗

我就是第二第三類的代表

Programming In Scala

Review 一下 重新熟悉一下

Digital Design with Chisel

2021-48

Composing Software

2021-47

第二次讀這本書

除了Transducer比較還沒有感覺外

其他的概念比較滲入了

我想我找這本書來Review

只是堅定信念 不要碰Java了

哈哈哈 

開打了 不是AZ 不是BNT 是Zelda Skyward Sword

PS.玩了幾個小時這個遊戲 

之前的海拉魯大地的拾荒者

比較好玩 只要會跑 就能玩

現在是海拉魯大地的砍草者

不好玩 一定要會使鐮刀 才能玩

UART Echo

Add UART->USB Converter

 

UART

Tx -> Hello World

Echo -> Rx -> Data -> Tx

https://gist.github.com/tzechienchu/35f4bfd044035b43ada9f9162ad21ef7

https://gist.github.com/tzechienchu/7d16f341b049f4ea66f1cbc58524ffc3

Since I don't have the UART ->USB converter. I can only rely on use simulation.

PS. I forget I got wio terminal. I should give it a try.

及時完成 薩爾達無雙的修復特拉寇任務

接下來就是 薩爾達 禦天之劍

PS.別弄錯這是第二次玩無雙 

Debounce

import chisel3._
import chisel3.util._

object MyLib {
    def FPGA_FREQ() = 50*1000*1000

    def sync(v: Bool) = RegNext(RegNext(v))
    def rising(v: Bool) = v & !RegNext(v)
    def tickGen(fac: Int) = {
        val reg = RegInit(0.U(log2Up(fac).W))
        val tick = reg === (fac - 1).U
        reg := Mux(tick, 0.U, reg + 1.U)
        tick
    }  
    def filter3(v: Bool, t: Bool) = {
        val reg = RegInit(0.U(3.W))
        when (t) {
            reg := Cat(reg(1,0), v)
        }
        (reg(2) & reg(1)) | (reg(2) & reg(0)) | (reg(1) & reg(0))
    }  
    def counter8(t: Bool) = {
        val reg = RegInit(0.U(8.W))
        when (t) {
            reg := reg + 1.U
        }
        reg
    }
    def sevenSeg(sw: UInt, dp: Bool) = {
        val sevSeg = WireInit(0.U(7.W))
        switch (sw) {
            is (0.U)  {sevSeg := "b0111111".U}
            is (1.U)  {sevSeg := "b0000110".U}
            is (2.U)  {sevSeg := "b1011011".U}
            is (3.U)  {sevSeg := "b1001111".U}
            is (4.U)  {sevSeg := "b1100110".U}
            is (5.U)  {sevSeg := "b1101101".U}
            is (6.U)  {sevSeg := "b1111101".U}
            is (7.U)  {sevSeg := "b0000111".U}
            is (8.U)  {sevSeg := "b1111111".U}
            is (9.U)  {sevSeg := "b1101111".U}
            is (10.U) {sevSeg := "b1110111".U}
            is (11.U) {sevSeg := "b1111100".U}
            is (12.U) {sevSeg := "b0111001".U}
            is (13.U) {sevSeg := "b1011110".U}
            is (14.U) {sevSeg := "b1111001".U}
            is (15.U) {sevSeg := "b1110001".U}
        }
        Cat(~dp,~sevSeg)
    }
} 

class Debounce extends Module {
    val io = IO(new Bundle {
        val btnIn = Input(Bool())
        val btnOk = Output(Bool())
        val btnOnce = Output(Bool())
    })
    val btnIn = io.btnIn

    val btnSync = MyLib.sync(btnIn)
    val tick = MyLib.tickGen(10*1000*1000)
    val btnDeb = Reg(Bool())
    when (tick) {
        btnDeb := btnSync
    }
    val btnOk = MyLib.filter3(btnDeb, tick)
    val btnOnce = MyLib.rising(btnOk)

    io.btnOk := btnOk
    io.btnOnce := btnOnce
}

class DebounceTop extends Module {
    val io = IO(new Bundle {
        val btnIn = Input(Bool())
        val hex2A = Output(UInt(16.W))
        val hex2B = Output(UInt(16.W))
    })
    val DebounceM = Module(new Debounce())
    val btnIn = io.btnIn
    val btnRawOnce = MyLib.rising(btnIn)

    DebounceM.io.btnIn := btnIn
    val btnOk = DebounceM.io.btnOk
    val btnOnce = DebounceM.io.btnOnce

    val counterA = MyLib.counter8(btnRawOnce)
    val counterB = MyLib.counter8(btnOnce)

    val Hex1 = MyLib.sevenSeg(counterA(3,0), 0.B)
    val Hex2 = MyLib.sevenSeg(counterA(7,4), 0.B)
    val Hex3 = MyLib.sevenSeg(counterB(3,0), 0.B)
    val Hex4 = MyLib.sevenSeg(counterB(7,4), 0.B)
    io.hex2A := Cat(Hex1, Hex2)
    io.hex2B := Cat(Hex3, Hex4)
}

object DebounceTop extends App {
    (new chisel3.stage.ChiselStage).emitVerilog(new DebounceTop())
}

https://gist.github.com/tzechienchu/c685156798ee5b4f0bced7b3e7e9e427

用 function generate hardware 真的感覺就是不一樣 

Quick Start Guide to Verilog

2021-46

疫苗護照是呆子的政策

疫苗護照之於Backend API

就像Query with Token 

難不成我Verify Token之後

認定你是好人 就讓你做你要做的事嗎

當然不是

程式內部該Check的還是依樣會 Check

意思就是

如果國內的人都打了疫苗

何必在意進來的人有沒有打

只有那些做事做一半的人 

會支持疫苗護照

那些我打疫苗了

我是特權了

我哪邊都要去

你們要給我去

讓我自由

而不在乎那些還人沒有打的人

或是還沒有打的國家

混蛋疫苗護照

花時間搞這個

不如趕快給國人 給全世界的人打疫苗

對於程式設計而言

寫一個安全的程式 比要求安全的資料 來的實在長久

Functional Programming Made Easier

看到1X章就讀不下去了 

必須要下來Coding 才會比較好

另外Purescript === Haskel

熟悉度也不夠

越後面越抽象 就越難看懂Code

找時間再來看

Value 很好懂

Type 也好懂

Function : Type -> Type 也好懂

Functor : MetaType -> MetaType 就不好懂了

(Map好懂 但是後來的.... Covariant ....就....)

PWM from Chisel Book

import chisel3._
import chisel3.util._

class PWM extends Module {
    val io = IO(new Bundle {
        val pwm = Output(Bool())
    })

    def pwmfn(nrCycles: Int, din:UInt):Bool = {
        val cntReg = RegInit(0.U(unsignedBitLength(nrCycles - 1).W))
        cntReg := Mux(cntReg === (nrCycles-1).U, 0.U, cntReg + 1.U)
        din > cntReg
    }
    
    val FREQ = 50*1000*1000
    val MAX = FREQ/1000
    val mReg = RegInit(0.U(32.W))
    val upReg = RegInit(true.B)

    when (mReg < FREQ.U && upReg) {
        mReg := mReg + 1.U
    } .elsewhen (mReg === FREQ.U && upReg) {
        upReg := false.B
    } .elsewhen (mReg > 0.U && !upReg) {
        mReg := mReg - 1.U
    } .otherwise {
        upReg := true.B
    }

    val pwm = pwmfn(MAX, mReg >> 10)

    io.pwm := pwm
}

object PWM extends App {
    (new chisel3.stage.ChiselStage).emitVerilog(new PWM)
}

https://gist.github.com/tzechienchu/691fccef3c241534c42976a2d6e9402a

Desing Digital System with SystemVerilog

2021-45

Review一下 SystemVerilog 接下來要來玩FPGA use Chisel

Why Chisel ?

因為當軟體工程師久了 懶了

能夠讓Code , do the job

就不要Copy Paste Modify

Accumulator with setValue(Key0~7) and setZero(Key8)

https://gist.github.com/tzechienchu/acb3d97799cf34471fbddc50d5d65c25

https://gist.github.com/tzechienchu/58ac6d61765560d957215b383db5d91d

I combine 3 Chisel3 Generate verilog file in TopD.v

Because Accumulator use 1hz clock generate by Timer block.

Need to study how to use different clock domain in Chisel3.

Why JWTs Suck <--- Hahahaha

https://scotch.io/bar-talk/why-jwts-suck-as-session-tokens

有人幫忙出氣 謝謝了@@

7 Segment Display

https://gist.github.com/tzechienchu/9558a2ebfa59d035411c6922e2dde75c

import chisel3._
import chisel3.util._

class SevenSegment extends Module {
    val io = IO(new Bundle {
        val sw = Input(UInt(4.W))
        val seg = Output(UInt(8.W))
        val dp = Input(Bool())
    })
    val sevSeg = WireInit(0.U)
    val sw = io.sw
    val dp = io.dp
    switch (sw) {
        is (0.U)  {sevSeg := "b0111111".U}
        is (1.U)  {sevSeg := "b0000110".U}
        is (2.U)  {sevSeg := "b1011011".U}
        is (3.U)  {sevSeg := "b1001111".U}
        is (4.U)  {sevSeg := "b1100110".U}
        is (5.U)  {sevSeg := "b1101101".U}
        is (6.U)  {sevSeg := "b1111101".U}
        is (7.U)  {sevSeg := "b0000111".U}
        is (8.U)  {sevSeg := "b1111111".U}
        is (9.U)  {sevSeg := "b1101111".U}
        is (10.U) {sevSeg := "b1110111".U}
        is (11.U) {sevSeg := "b1111100".U}
        is (12.U) {sevSeg := "b0111001".U}
        is (13.U) {sevSeg := "b1011110".U}
        is (14.U) {sevSeg := "b1111001".U}
        is (15.U) {sevSeg := "b1110001".U}
    }
    io.seg := Cat(~dp,~sevSeg)
}
object SevenSegment extends App {
    (new chisel3.stage.ChiselStage).emitVerilog(new SevenSegment())
}

Chisel Simulation to GTKWave

Goroutine 讓我想到 Transputer

https://en.wikipedia.org/wiki/Transputer

不知道還有沒有人知道這個東西

我還有他的Evaluation Board. 塞在某個櫃子裡

最近學的Goroutine 讓我又想到這顆IC

找找看有沒有FPGA的Verilog.

老工程師大概東西看多了 所以有甚麼新Idea 感覺不會很興奮

太陽底下新鮮事越來越少 就是老了@@

不過有趣的東西會不斷的轉變

只要知道他的本質

雖然不是新鮮事 但是還是有趣的事

Mastering Go

2021-44

 

對啦 你就喜歡新東西@@

"我有嗎? 好像?"

跟幾年不見的同學在 LINE上 聊了一下天

就像面試般的 說明了一下自己最近的工作情況

同學脫口而出

仔細想想自己曾經工作過的Legacy System

一個打掉重做

一個也是打掉重做

一個跑掉不敢做 才?天

一個跑掉做不了 才?個月

好像喔

其實Legacy System 最大的問題不是 System

跑掉的原因是因為我無法跟Legacy Peopel一起Work.

甚麼是Legacy Peopel. 舉例來說

之前有公司找我去寫Java 我說要的話就寫Scala

Legacy People 當然不要  

不過我也能接受啦 畢竟如果系統都是Java

然後有一些是Scala到時要找人 麻煩

問題是對我而言 Java應該就讓它就消失

之後就只使用Scala這樣就沒有維護的問題了

哈哈哈哈

不願意嘗試新東西的 就是Legacy People

我是遇過比較多Legacy Engineer

老闆才不在乎@@

Legacy Cat or Fancy Cat 

Catch Mouse is Goog Cat

But to Fancy Cat

How to Catch 

is more important than

Catch 

 

 

DE10-Lite Hello World

OS: Linux Ubuntu 20.10

Board : DE10-Lite

Quartus Prime Lite 20.x

Top.v -> Hello.v (Generate from Chisel)

Issues:

1.Setup USB Blaster in Linux

https://rocketboards.org/foswiki/Documentation/UsingUSBBlasterUnderLinux

2.Don't use Quartus's Project Wizard Board Selection. (De10-Lite Chip is wrong)

3.When thing goes wild, check the Pin file setting

4.Use the Pin file and sdc file from the De10-lite board CDROM (download from Terasic)

Go Programming 入門

2021-43

10分鐘的傳記

2021-42

Hardcore Functional Programming In JavaScript V2

有V2 繼續複習下去

Before FP, we compose state (variable assigment)

After FP, we compose function with type.

TinyGo Goroutine on Wio Terminal (3)

https://gist.github.com/tzechienchu/3685e7a2b6680b86f11eaaa4bc03e98c

Add Channel Fork and Buffer Filler

Create DIY Microcontroller Project with TinyGo and WebAssembly

2021-41

關於Goroutine談的比較少 很可惜 還是傳統的那套

Goroutine on Wio Terminal (2)

https://gist.github.com/tzechienchu/3685e7a2b6680b86f11eaaa4bc03e98c

func pinDebounce(
	done <-chan interface{},
	pin machine.Pin,
	delay time.Duration,
) <-chan bool {
	pStream := make(chan bool)
	btnV := [2]bool{false, false}
	go func() {
		defer close(pStream)
		for {
			v1 := !pin.Get()
			btnV[0] = v1
			select {
			case <-done:
				return
			case pStream <- btnV[0] && btnV[1]:
			}
			time.Sleep(time.Duration(delay) * time.Millisecond)
			btnV[1] = btnV[0]
		}
	}()
	return pStream
}
func readLightSensor(
	done <-chan interface{},
	delay time.Duration,
) <-chan uint16 {
	sensor := machine.ADC{Pin: machine.WIO_LIGHT}
	sensor.Configure(machine.ADCConfig{})
	pStream := make(chan uint16)
	go func() {
		defer close(pStream)
		for {
			val := sensor.Get()
			select {
			case <-done:
				return
			case pStream <- val:
			}
			time.Sleep(time.Duration(delay) * time.Millisecond)
		}
	}()
	return pStream
}
func lowPass(
	done <-chan interface{},
	vStream <-chan uint16,
) <-chan uint16 {
	iStream := make(chan uint16)
	his := uint16(0)
	fir := func(val uint16) uint16 {
		his = (his * 9 / 10) + (val * 1 / 10)
		return his
	}
	go func() {
		defer close(iStream)
		for v := range vStream {
			select {
			case <-done:
				return
			case iStream <- fir(v):
			}
		}
	}()
	return iStream
}

Use Goroutine is so easy to compose different IO.
Latter will add a state machine use goroutine.

書是唯一尚未受到褻瀆腐化的媒體

其他

在你眼皮底下的媒體

無一不是在拿廣告操縱你

by 納西姆 尼可拉斯 塔雷伯 

Concurrency In Go

2021-40

TinyGo Goroutine Test on WioTerminal

I try the code TinyGo on Wio Terminal to feel the operation of goroutine 
It is not a preemptive time-share style thread.
So ... beware of long runnung operation.

Following is Simulation of Running Operation
	primeFinder := func(
		done <-chan interface{},
		iStream <-chan int,
	) <-chan interface{} {
		pStream := make(chan interface{})
		go func() {
			defer close(pStream)
			for iV := range iStream {
				iV -= 1
				prime := true
				for d := iV - 1; d > 1; d-- {
					if iV%d == 0 {
						prime = false
						break
					}
				}
				if prime {
					select {
					case <-done:
						return
					case pStream <- iV:
					}
				}
			}
		}()
		return pStream
	}

PS. Use tinygo on wio terminal feel nicer than rust. :(

Hardcore Functional Programming In JavaScript

2014/2015年時上的課

真的是感謝Brain介紹 進入Functional 的世界

重新認識Computation

進而學習Scala 認識Type System

這些基本的要常常Review

Go In Action

2021-39

Go或許是個簡單的語言 但是CSP並不是

應該用心研究一下Golang 的Channel 與 Goroutine

畢竟沒有Goroutine 就沒必要學Go