Accumulator with setValue(Key0~7) and setZero(Key8)

https://gist.github.com/tzechienchu/acb3d97799cf34471fbddc50d5d65c25

https://gist.github.com/tzechienchu/58ac6d61765560d957215b383db5d91d

I combine 3 Chisel3 Generate verilog file in TopD.v

Because Accumulator use 1hz clock generate by Timer block.

Need to study how to use different clock domain in Chisel3.