Verilog

Why I use migen/Amaranth as HDL , instead of Verilog. 

Because:

Verilog is not good at data encapsulation. 

It is messy when you try to wiring stuff together.

It lack modern language feature like namespace to help you module your code.

Use python you treat wire as data , you can move it around, pass it around.

Group wire together, manipulate them as whole.

It make the code easy to read and debug.

You will see latter.

Verilog is  Assembly code for Synthesizer to generate gateware. 

migen/Amaranth are C code  for People to read.